Thermal oxidation of silicon converts a portion of exposed silicon into thermal silicon oxide as oxygen atoms diffuse into the silicon material. The volume of the resulting thermal silicon oxide is greater than the volume of the initial silicon region since the incorporated oxygen atoms induce volume expansion, which applies a compressive stress to the remaining silicon material.
Use of thermal silicon oxide as a liner in shallow trench isolation is known the in the art. Referring to FIG. 1, an exemplary prior art structure comprises a semiconductor substrate 8, a p-type field effect transistor (PFET) region 100, and an n-type field effect transistor (NFET) region 200. The semiconductor substrate 8 is a semiconductor-on-insulator substrate containing a handle substrate 10, a buried insulator layer 20, and a top semiconductor layer 30. The top semiconductor layer 30 comprises a PFET active area 22, an NFET active area 24, and a boundary semiconductor region 26, each of which is separated from the rest by shallow trench isolation 62 and a thermal silicon oxide liner 51 having a thickness t0. A PFET comprises the PFET active area 22 and the collection of a gate dielectric 70, a gate conductor 72, and a gate spacer 74 thereupon within the PFET region 100. Likewise, an NFET comprises the NFET active area 24 and the collection of a gate dielectric 70, a gate conductor 72, and a gate spacer 74 thereupon within the NFET region 200.
Since the thermal silicon oxide liner 51 has the same thickness t0 throughout the exemplary prior art structure, the PFET active area 22 and the NFET active area 24 are subjected to the same lateral compressive stress effect due to the thermal silicon oxide liner 51. While the level of lateral compressive stress is determined by the size and geometry of the PFET active area 22 and the NFET active area 24 and the thickness of the thermal silicon oxide liner 51, the mechanism for generation of the lateral compressive stress is the same across the PFET region 100 and the NFET region 200. Thus, for a PFET active area 22 and an NFET active area 24 having identical geometry, the magnitude and the direction of the lateral compressive stress is the same.
When stress is applied to the channel within an active area of a semiconductor transistor, the mobility of carriers, and as a consequence, the transconductance and the on-current of the transistor are altered from their corresponding values for a transistor containing an unstressed semiconductor. This is because the applied stress and the resulting strain on the semiconductor structure within the channel affects the band gap structure (i.e., breaks the degeneracy of the band structure) and changes the effective mass of carriers. The effect of the stress depends on the crystallographic orientation of the plane of the channel, the direction of the channel within the crystallographic orientation, and the direction of the applied stress.
The effect of uniaxial stress, i.e., a stress applied along one crystallographic orientation, on the performance of semiconductor devices, especially on the performance of a metal-oxide-semiconductor field effect transistor (MOSFET, or a “FET” in short) device built on a silicon substrate, has been extensively studied in the semiconductor industry. For a p-type MOSFET (PMOSFET, or a “PFET” in short) utilizing a silicon channel, the mobility of minority carriers in the channel (which are holes in this case) increases under uniaxial compressive stress along the direction of the channel, i.e., the direction of the movement of holes or the direction connecting the drain to the source. Conversely, for an n-type MOSFET (NMOSFET, or an “NFET” in short) devices utilizing a silicon channel, the mobility of minority carriers in the channel (which are electrons in this case) increases under uniaxial tensile stress along the direction of the channel, i.e., the direction of the movement of electrons or the direction connecting the drain to the source. These opposite requirements for the type of stress for enhancing carrier mobility between the PMOSFETs and NMOSFETs have led to prior art methods for applying at least two different types of stress to the semiconductor devices on the same integrated chip.
Typical MOSFET devices have an active area in the shape of a rectangular block having a length in the direction of a channel and a width in the direction perpendicular to the direction of the channel, in which the width is greater than the length. A thermal silicon oxide liner surrounding the active area of a PMOSFET applies a laterally compressive stress along the direction of the channel of the PMOSFET, and thus advantageous to performance of the PMOSFET through enhancement of hole mobility and on-current of the PMOSFET. The thermal silicon oxide liner surrounding the active area of an NMOSFET also applies a laterally compressive stress along the direction of the channel of the NMOSFET. However, the lateral compressive stress is disadvantageous to the performance of the NMOSFET through degradation of electron mobility and reduction of on-current of the NMOSFET.
In view of the above, there exists a need for a semiconductor structure that provides the advantageous effects of a thermal silicon oxide liner on a PMOSFET, while minimizing the adverse effects of the thermal silicon oxide liner on an NMOSFET, and methods of manufacturing the same.
Also, there exists a need for a semiconductor structure providing such benefits described above on a PMOSFET and an NMOSFET formed on an ultrathin semiconductor-on-insulator substrate and methods of manufacturing the same.
Also, there exists a need for a semiconductor structure in which the lateral compressive stress on the PMOSFET is at a high level to advantageously affect the performance of the PMOSFET, while avoiding an adverse effect on the performance of the NMOSFET.